The present invention relates generally to the field of computer-aided design (CAD) systems and methods, and in particular to CAD systems and methods for digital circuit design and verification.
Computer-aided design of digital circuits and other complex digital systems is widely prevalent. In such computer-aided design, circuits and systems are usually designed in a hierarchial manner. The requirements of the circuit or system are defined in an abstract model of the circuit or system. The abstract model is then successively transformed into a number of intermediate stages. These intermediate stages often include a register transfer level model which represents a block structure behavioral design, and a structural model which is a logic level description of the system. Eventually a transistor net list and consequently the physical layout of the circuit or system are derived.
The design of the circuit or system therefore proceeds from the general requirements level to the lower detailed level of a physical design, interposed between which are a number of intermediate levels. Each successive level of the design is tested or verified to ensure that the circuit or system continues to meet the design requirements. It is highly desirable to verify each level in the design as errors in one level of the design that are not corrected until after further levels have been designed drastically increases the cost of correcting such errors. Thus, it is important to test each level of the design against the requirements. As each level of the design is tested against the requirements, this task resolves to the task of comparing each level of the design to the prior level of the design. This testing of succeeding levels against immediately preceding levels can also be intuitively seen when it is realized that each succeeding level is often merely an optimization of the preceding level. Thus, the testing or verification of circuit designs can, to an extent, be viewed as similar to checking the backward compatibility of successive generations of circuits or systems.
Binary decision diagrams (BDDs) have been used to solve CAD related problems. These problems include synthesis problems, digital-system verification, protocol validation, and generally verifying the correctness of circuits. BDDs represent Boolean functions. For example, FIG. 1 shows a circuit comprising first and second OR gates 11, 13, and an AND gate 15. The first OR gate has inputs N1 and N2. The second OR gate has inputs N2 and N3, with input N2 being shared by the two OR gates. The outputs of the OR gates are fed into the AND gate. The AND gate has an output N6. Thus, the output of the AND gate can be represented by the boolean function N6=(N1 OR N2) AND (N2 OR N3).
A BDD for this circuit is shown in FIG. 2. The BDD is composed of vertices, which may also be called nodes, and branches. Vertices from which no further branches extend are termed terminal vertices. The BDD is an Ordered BDD (OBDD) as each input is restricted to appearing only at one level of the BDD. The BDD may be reduced to a Reduced OBDD (ROBDD) as shown in FIG. 3. The rules for reducing OBDDs are known in the art. These rules include eliminating redundant or isomorphic nodes, and by recognizing that some nodes can be eliminated by exchanging the branches of a node with a node or its complement. The importance of ROBDDs is that ROBDDs are unique, i.e., canonical. Thus, if two OBDDs reduce to the same ROBDD, the circuits represented by the OBDDs are equivalent.
In most applications, ROBDDs are constructed using some variant of the Apply procedure described in R. E. Bryant, Graph-Based Algorithms For Boolean Function Manipulation, IEEE Trans. Computer C-35(8): 667-691, August 1986, incorporated by reference herein. Using the Apply procedure the ROBDD for a gate g is synthesized by the symbolic manipulation of the ROBDDs of gate g""s inputs. Given a circuit, the gates of the circuit are processed in a depth-first manner until the ROBDDs of the desired output gates are constructed.
A large number of problems in VLSI-CAD and other areas of computer science can be formulated in terms of Boolean functions. Accordingly, ROBDDs are useful for performing equivalence checks. A central issue, however, in providing computer aided solutions and equivalence checking is to find a compact representation for the Boolean functions so that the equivalence check can be efficiently performed. ROBDDs are efficiently manipulable, and as previously stated, are canonical. In many practical functions ROBDDs are compact as well, both in terms of size (memory space) and computational time. Accordingly, ROBDDs are frequently used as the Boolean representation of choice to solve various CAD problems.
ROBDDs, however, are not always compact. In a large number of cases of practical interest, many ROBDDs representing a circuit or system described by a Boolean function may require space which is exponential in the number of primary inputs (PIs) to the circuit or system. This makes solving for equivalence an NP-hard problem. The large space requirement, either in terms of memory or computational time, places limits on the complexity of problems which can be solved using ROBDDs.
Various methods have been proposed to improve the compactness of ROBDDs. Some of these methods improve compactness, but do not maintain canonicity and manipulability of the ROBDDs. Such methods reduce the applicability of the use of ROBDDs. Other methods, which maintain canonicity and manipulability, represent the function over the entire Boolean space as a single graph rooted at an unique source. A requirement of a single graph, however, may still result in ROBDDs of such a size that either memory or time constraints are exceeded.
Methods of reducing the size of ROBDDs have been proposed. The size of an ROBDD is strongly dependent on its ordering of variables. Therefore, many algorithms have been proposed to determine variable orders which reduce the size of ROBDDs. For some Boolean functions, however, it is possible that no variable order results in a ROBDD sufficiently small to be useful, or that no such variable order can be efficiently found.
The space and time requirements of ROBDDs may also be reduced by relaxing the total ordering requirement. A Free BDD is an example of such an approach. A Free BDD (FBDD) is a BDD in which variables can appear only once in a given path from the source to the terminal, but different paths can have different variable orderings.
Another approach to obtain a more compact representation for Boolean functions is to change the function decomposition associated with the nodes. Generally, a BDD decomposition is based on the Shannon Expansion in which a function ƒ is expressed as xƒx+{overscore (x)}ƒ{overscore (x)}, or methods derived from the Shannon expansion such as the Apply method. Some other decompositions include the Reed-Muller expansion, or the use of expansion hybrids such as Functional Decision Diagrams (FDDs), or through the use of Ordered Kronecker Functional Decision Diagrams (OKFDDs). All of these methods, however, represent a function over the entire Boolean space as a single graph rooted at a unique source. Thus, these methods still face problems of memory and time constraints.
Furthermore, many designs, particularly for sequential circuits, are not adequately verified. Usually a test-suite is prepared to test such designs. The test-suite includes a number of test cases in which the design is subjected to varying combinations of assignments for the primary inputs of the design. A single combination of assignments for the primary inputs forms an input vector. A sequence of input vectors, used to test designs having sequential elements such as flip-flops, forms a test vector.
Test-suites are often prepared by engineers with specialized knowledge of the design being tested. Therefore test-suites are useful test devices. However, test-suites only test a very small portion of a state or Boolean space of the design. For designs with an appreciable number of primary inputs or possible test vectors, test-suites do not test a substantial portion of input vectors or test vectors of particular interest.
The present invention provides a method and system for evaluating digital circuits and systems that are otherwise unverifiable through the use of BDD-based verification techniques using windows of Boolean space representations of the digital circuits and systems. In a preferred embodiment, the digital circuit or system is represented as a Boolean function forming a Boolean space. The Boolean space is partitioned into partitions, which may be recursively partitioned into still further partitions. Partitions which are otherwise too large for the formation of a BDD are expressed in terms of a decomposed partition string having components or elements combinable to form the partition. These components or elements are combined in a scheduled order. If any of the combinations result in zero then the decomposed partition string also results in zero. Thus, combining all of the components or elements is unnecessary if any sub-combination results in zero, thereby allowing evaluation of the partition represented by the decomposed partition string.
Accordingly, the present invention provides a method and system of verifying the equivalence of first and second circuits. The first and second circuits have corresponding sets of primary inputs and primary outputs. The first and second circuits are represented as Boolean functions and a Boolean space is represented by exclusive ORing the corresponding outputs of the Boolean functions. In building a decomposed Binary Decision Diagram for the Boolean space the Boolean space is partitioned during composition of a decomposition point when the Binary Decision Diagram resulting from composition exceeds a predetermined constraint on computer memory usage. The circuits can then be determined to be equivalent if all of the resulting partitions are zero.
Moreover, the present invention provides a sampling method for use in the partial verification of otherwise unverifiable circuits, systems, and designs thereof. The state space of the circuit, system, or design is partitioned into multiple partitions. These partitions are formed through any of several be methods, including methods that analyze test-suites for the circuit, system, or design. Additionally, if an intermediate BDD exceeds predefined constraints on memory usage the BDD can be replaced with a zero terminal vertice and other partitions of the state space evaluated.
These and other features of the present invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.